www.austriamicrosystems.com/AS5115
Revision 1.11
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AS5115
Datasheet - Electrical Characteristics
6.1 Timing Characteristics
Remark: The digital interface will be reset during the low phase of the CS signal.
VOUT
Analog output range
VSS + 0.25
VDD - 0.5
V
IOUT
Output Current
-1
1
mA
CLOAD
Capacitive Load
1000
pF
Table 7. Timing Characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Unit
t1_3
Chip select to positive edge of DCLK
see Figure 5 and
Figure 6
30
-
ns
t2_3
Chip select to drive bus externally
0
-
ns
t3
Setup time command bit
Data valid to positive edge of DCLK
30
-
ns
t4
Hold time command bit
Data valid after positive edge of DCLK
15
-
ns
t5
Float time
Positive edge of DCLK for last
command bit to bus float
-
ns
t6
Bus driving time
Positive edge of DCLK for last
command bit to bus drive
-
ns
t7
Data valid time
Positive edge of DCLK to bus valid
ns
t8
Hold time data bit
Data valid after positive edge of DCLK
-
ns
t9_3
Hold time chip select
Positive edge DCLK to negative edge
of chip select
-
ns
t10_3
Bus floating time
Negative edge of chip select to float
bus
-
30
ns
t11
Setup time data bit at write access
Data valid to positive edge of DCLK
30
-
ns
t12
Hold time data bit at write access
Data valid after positive edge of DCLK
15
-
ns
t13_3
Bus floating time
Negative edge of chip select to float
bus
-
30
ns
Table 6. Electrical System Specifications
Symbol
Parameter
Condition
Min
Typ
Max
Unit
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